What would semiconductor chips say if every chip had its own “VOICE” and communicated in a variety of languages? Would self-driving cars talk among themselves rendering traffic a thing of the past? And would they continuously monitor and discuss their conditions and their life expectancies? Would chips be programmed to communicate directly with Advantest testers using their native languages? Listen in as Steve Pateras, vice president of marketing and strategic business development at Synopsys, Klaus Dieter Hilliges, Advantest 93000 platform extension manager, and I, Keith Schaub, vice president of technology and strategy at Advantest, discuss this revelation and some of the many innovations being showcased at the annual Advantest VOICE developer conference taking place May 17-18th 2022 at the OMNI Montelucia in Scottsdale, Arizona.
DAVID EAGLEMAN: Hi this is David Eagleman. I'm a neuroscientist at Stanford University and an author and the co-founder of the brain machine interface company, Neosensory. I want to give you a sneak peek of my talk at VOICE 2022. I'm going to talk about how the brain works and its biggest mysteries, and I'm also going to talk about our company's electronics and how we've pulled off a new way to pass information to the brain using brain machine interfaces. And more generally, I'm going to talk about innovation and what's happening under the hood when we create new ideas and build new kinds of products. So, I look forward to seeing you at VOICE 2022.
KEITH SCHAUB: This week on Advantest Talks Semi we have a special episode leading up to our annual VOICE Developer Conference. The event takes place May 17th and 18th at the Omni Montelucia in Scottsdale, Arizona. Themed Beyond the Technology Horizon, VOICE brings together semiconductor test professionals representing the world's leading IDM foundries, FABless and OSAT providers to discuss the latest technology advancements. Steve Pateras, Vice President of Marketing and Business Development at Synopsys, will be delivering one of the keynotes at VOICE and has graciously agreed to give us a sneak peek of some of Synopsys’s innovations that he will be discussing before the live audience. Steve, welcome to Advantest Talks Semi.
STEVE PATERAS: Hi Keith. Thanks for having me.
KEITH SCHAUB: Steve, in a world fast becoming smart everything, powering this new era of innovation are high performance silicon chips and exponentially growing amounts of software content. Synopsys plays a major role with the world's most advanced technologies for chips and one of these new concepts that you're going to be talking about at VOICE is Silicon Lifecycle Management (SLM). Tell us about that.
STEVE PATERAS: Yeah, so as you said, our world is becoming fully digitized. You know, every aspect of our economy really relies on electronic semiconductor products and that means that these products really need to perform at a very high level. So we're seeing, you know, growing need for all kinds of increased metrics for each of these capabilities. So think of, you know, not only performance but reliability and safety, security, low power, and what we've realized is that you cannot guarantee all these metrics through design only. We realized that we had to go beyond what we refer to as tape-out, right. We needed to be able to be involved with that chip throughout its life and that's sort of what was the impetus for creating this concept of Silicon Lifecycle Management. And then the whole idea here is that we need to be able to actively monitor and manage semiconductor electronic devices as a whole throughout their lifecycle. So historically, I'm part a DFT and test team. Right? So, we created abilities to test semiconductor devices after tape-out with manufacturing test, and what we realized is as time went on there was a need or request from our customers to testing beyond just manufacturing phase. So, we got into things like power on test and that was very prevalent in automotive. Right? So, when every time you turn on your car, you want to test it. So, you need to run some kind of embedded test. And then that grew into, well if you're testing it when I turn on my car, can you now test periodically for increased reliability? And if you can do that, can you start, can you test continuously, and if you're testing continuously, can you start monitoring for other issues? And that is really what Silicon Lifecycle Management is all about, is really this ability to continuously monitor and manage semiconductor devices. And so SLM, really at its core, is really two things. It’s instrumentation. So, it's adding the ability to observe silicon and the way we do that is by adding all types of monitors and sensors into the device. We have the ability to be able to insert all types of monitors and sensors in a very seamless way that does not affect design performance. So, once you have that instrumentation, that visibility, you then want to be able to take advantage of it. So, you want to be able to extract information from the chip and you want to be able to analyze and understand what's going on. So, that's the other part of SLM. Right? Or Silicon Lifecycle Management. That's the analytics part. So, what observability and analytics. We want to be able to do that throughout the life and analyze it to understand what's going on inside that chip and then to react. Do we need to disable part of the chip? So, if it's getting too hot, we need to lower the frequency. If there's some activity that is questionable, do we need to turn off access to parts of the chip? So, this is what SLM is all about.
KEITH SCHAUB: Steve, how do you see this helping the product and test engineers, for example, with yield ramp improvement or with manufacturing optimization?
STEVE PATERAS: The beauty about SLM is that once you have this data, this visibility you can really use it for doing so many different things throughout the life cycle. I can improve the design performance. I can, you know, I can reduce marginality, can improve how performance when it's operating in the field. But for this audience here at VOICE, I have tons of improvements we can do during yield ramp and in production test having that kind of visibility, and it's really two things. But it's having that invisibility, but also having this wealth of data that we that we accumulate not only within a particular die but across dies and wafers and lots over time because then we can start looking at trends. So, for example, during yield ramp, first of all, I can use additional information. So, if I not only do I have test information but if I have now voltage information, so, you know, changes in voltage across the chip, changes in temperature across the chip, I can understand differences in process across the chips. You know, past delays, I can start correlating that to my test results and it gives me a better understanding of what's going on inside the chip. I can, for example, I can do outlier detection. Right? So, a test may pass for example, but if I see that during that test that I had this voltage spike, I may decide to label that part as an outlier and discard it. Another example is, I have failures in the field. If I bring out those failures back, I can now correlate that failure and that device to wafer, to which lot that was part of. If there are failures from other devices in that way for, that'll help me understand this particular failure mechanisms enhance and improve the yield. So, it's both this observability, having more kinds of information, you know, as I said, very environmental data like voltage and temperature and process variations but also having this large amount of information data, cross wafers and time, allowing me then to look at correlations and trends and improve my ability to improve yield or even reduce test cost.
KEITH SCHAUB: What I'm hearing, and to use a medical analogy, we have all of this genealogy data now at our disposal. So, we have parent data, child data, derivatives, aunts, uncles, cousins and utilizing all of that data, we can make better decisions and better plans for the performance and health of that device over its life. For example, if there's something historically in the medical records, the doctor will put in place additional tests to monitor for that. Whereas if the individual is perfectly healthy and there's nothing in the medical genealogy or history, then those tests get skipped and we don't need it.
STEVE PATERAS: Yeah, that is a great example. And in fact, what you're sort of referring to the analogy in our space and the test bases, adaptive testing. Right? So, I can change what I'm doing on a per die, on a per wafer per lot, based on that understanding what's going on at a global scale. So, having that the genealogies you say, or the traceability, and that ability to predict what's going on allows me to adapt my test. I can either do more testing if the chip is an outlier, I can do less testing and save cost if I realize that this device is well within various parameters and is unlikely, or I know will not be an issue down the line.
KEITH SCHAUB: What sort of changes do you expect or are we seeing on the manufacturing test floors to accommodate these new data streams, whether it's data feed forward, data feed backward, live data, streaming data. What are you seeing?
STEVE PATERAS: Absolutely. And so, you know, we were talking about a paradigm shift here, right? Going from a traditional bunch of test patterns of being applied to an individual die and looking at the results very often offline to one where we want to be able to have this richness of data. So, we need to create essentially sort of a data superhighway. The device under test and the analytics capabilities wherever they may be, and typically they would be in the cloud. In order to achieve that, there’s a lot of infrastructure that is needed to create that pathway and it's a bidirectional pathway. Right? So, I want to be able to extract large amounts of data from the DUT through the test from the test floor up into the cloud to where I'm doing analytics. And once I have information about resulting from those analytics, I want to be able to potentially go back the other direction and affect what I'm doing to the DUT. So, there was this whole idea of adaptive test. So, there are a lot of components to that and you know we've been working with Advantest on many of these and of course Advantest has been working in that area as well. So, at the lowest levels is the DUT itself, so how do I get all this information out? This requires a lot of bandwidth. So, we need to really change again the paradigm there from more of a traditional test IO data extraction mechanism to one that is a very high bandwidth. So, we've developed this concept of high speed IO interfaces where we use functional interfaces to extract data like USB or PCI express multi gigabit per second interfaces allowing us to bring out a lot of data in a short amount of time. That requires changes on the tester. The audience may be aware of Advantest Link Scale™ high speed interfaces now that support this kind of high-speed interface activity. We need software to be able to understand this high-speed data because this high-speed data is coming as packets. It's no longer just you know, ones and zeros. It's now packetized information through a PCI USB interface so, we need to be able to depacketize that interpret that data. So, you need softer running on the tester and then you need to then send this data off somewhere. And so, for example, Advantest Nexus™ data streaming capabilities were working with Advantest on that to connect our depacketized data interpretation software to then blow this through the Nexus environment to the cloud. And on the cloud end, we have our analytics or our other third party links that could be used there of course, but Synopsys has their own that's doing all this production analytics and then you want to be able to come back. Now, what I've described is, if you go all the way up into the cloud, it's basically a high latency providing course changes to our test strategy. So, maybe between wafers, between lots, you're looking at making changes. But, there's also you also want to have the ability to do things faster. So very, very low latency. And so, you may want to move your analytics from the cloud to the actual test cell to the test floor to test cell itself. Right, so Advantest’s New ACS Edge™, for example, the ability to have analytics running in the test cell itself to have this very low latency. So, we're working with Advantest on that as well. So being able to to add some analytics local to the tester that is using this information to be able to make decisions very, very quickly and you know, in microseconds in order to change what's going on within a particular insertion or potentially at least across individual die.
KEITH SCHAUB: Well Steve, I want to thank you again for coming on today and giving us an early sneak peek into some of the Synopsys innovations that you will be discussing at this year's VOICE 2022 Conference.
STEVE PATERAS: Great! Thank you so much for having me, Keith. Look forward to seeing everybody at VOICE as well.
KEITH SCHAUB: At this year's Advantest VOICE Developer Conference, themed Beyond the Technology Horizon, you'll see many new innovations. One of those innovations is the new Link Scale™, which is a family of digital channel cards for the V93000 platform enabling software based functional testing and USB PCI express scan testing of advanced semiconductors. I'm joined by Klaus-Dieter Hilliges, Platform Extension Manager, to give us a better understanding of what are the major trends and challenges that are driving these new innovations. Welcome Klaus-Dieter.
KLAUS-DIETER HILLIGES: Thanks Keith, appreciate the chance to speak to you and all.
KEITH SCHAUB: So, Klaus, let's dive right in. The semiconductor industry is going through a massive expansion right now and there are major trends that we're seeing in semiconductor test, lots of new opportunities, lots of existing and new challenges. What are you seeing?
KLAUS-DIETER HILLIGES: Yes, there is actually a lot more dynamics in the market than there has been for years. And one of the trends that is in everybody's understanding is the explosion of scan data volume we have to test, and that leads, of course, to more vector memory being needed, more longer test times. Right? And on the other hand, we lack the GPIOs, we lack the interfaces we used to test through. Devices come with lots more high-speed IO. But using them for traditional scan is hard, so we have to test through high speed IO.
KEITH SCHAUB: I guess a lot of the new designs, they're just minimizing pins and we're starting to lose pin access so that even if we could transmit more data, we just don't have the access.
KLAUS-DIETER HILLIGES: Right, right. And actually, a good point to be more clear here. On the package side, we have now so complex packages with comprehensive, for example, high bandwidth memory stacks inside that from the outside you don't have DDR interfaces, for example anymore. Literally, you only have high speed interfaces, very few things beyond with an insufficient overall bandwidth for classical kind of parallel IO pins. But on the other hand, you have these chiplets that are inside of that chip in this package. Those again don't even have the strength to be able to drive out. So, also there we need to come up with better solutions to drive the scan content through them.
KEITH SCHAUB: So, what else are you seeing?
KLAUS-DIETER HILLIGES: Yeah, I guess we had Steve mentioned this before, we want all drive, self-driving cars, right? A lot more mission critical applications we develop our products into and those need new coverages in the field, in the systems you drive a car and the car ASIC test itself while you drive. And that means we have to be able to test for those functional high-speed IO interfaces. Right? I mean the car is in the operation, there is no test port for that. And accordingly, just like Steve described, we need to be able to test, for example through PCIe, which is what we collaborate on.
KEITH SCHAUB: I see. So, these coverage gaps with scans, how do we do that structurally versus functionally?
KLAUS-DIETER HILLIGES: Yeah, good one. So, we talked about scan and it is the workhorse for test coverage. It's what the industry depends on. It's the basic for quality, no doubt about that. But beyond that, we see various people described this in paper that scan is not sufficient. Maybe some of you have heard papers from Google, from Facebook. They talk about silent data corruption. In the data center of theirs, they see perfectly good parts, so they're not defective. There wasn't a scan coverage gap, suddenly calculating wrongly, right? And why is that? Well, the conditions that this device is operated in maybe the workload, maybe the temperature, is so different from the scan application that that's what we need to functional test for. And we see this, of course, as many people move to system level tests to get coverage, trying to find ways of getting that coverage. But of course, system level test is late in the process. What would I do on a chiplet? Right?
KEITH SCHAUB: I guess there's some new innovations that we're going to be talking about at VOICE that helped to address a lot of these new challenges. So, let's jump into those.
KLAUS-DIETER HILLIGES: Absolutely. So firstly, we have to remember last year we introduced the extra scale generation of the V93000 with its evolutionary but critical extensions of what we classically do on tests. So, we have very much deeper vector memory, right? We have the highest performance, 5 gigabit per second data rates that we can drive through. And of course, we have a new power supply that drives people through ganging way beyond the 1000 amps and we need those, right? It's part of the trends that we saw of course, as the voltage rail goes down the current consumptions go up. So, this is the foundation, the workhorse that we extend and will be the leading generation in the market soon again. Now beyond that, we worked on new product that allows us to test through USB or PCIe, and Steve mentioned that a good part of that was in collaboration with Synopsys where we strive to test scan, let's say through PCIe, and we also use it for functional test. Right? As I mentioned earlier, coverage gap, Link Scale™ offers that as well.
KEITH SCHAUB: That's amazing. So basically, we get a new conduit to facilitate faster transfer of data in vectors to and from the device pretty much at speed.
KLAUS-DIETER HILLIGES: That's right. That's right. Yes, we have customers now they do and say, hey, I have no GPIO, I must move to scan over PCIe. Of course, once you say that, the problem becomes the internal fabric much more than the bandwidth on the PCIe, which is of course enormous. Right? Takes 16 lanes of gen 3. That's an enormous bandwidth for PCIe. The challenge becomes the inside of the chip and again, we work together with the EDA partners to get that fabric in place and Link Scale™ can feed that data volume. Right? And that's what it was built for.
KEITH SCHAUB: So, Klaus-Dieter, I want to thank you for sharing some exciting new innovations being showcased at the Advantest VOICE 2022 Developer Conference.
KLAUS-DIETER HILLIGES: Sure, thank you very much. Have a great time at VOICE.
KEITH SCHAUB: Registration is currently open but, closing soon. Find out how you can attend VOICE in person, visit voice.advantest.com. Hope to see you live in person next month at VOICE. That does it for another episode of Advantest Talks Semi. See you next time.
Note: This transcript was partially created with the assistance of AI from AWS Transcribe.