Advantest Talks Semi

Extreme Ultraviolet (EUV) lithography: Going beyond 2nm

• Keith Schaub Vice president of Technology and Strategy at Advantest, Mr. Toshimichi Iwai, Senior Vice President of E-Beam Lithography at Advantest's R&D facility • Season 2 • Episode 4

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Producing the world's most complex and advanced semiconductors isn't rocket science; it's far more difficult and getting tougher. For example, today's most advanced AI devices are made using a 5nm process. 5nm, which in layperson's terms, is equivalent in size to two DNA strands. Imagine somehow placing billions of strands of DNA in an exact and elaborate pattern, 100 layers high, in an area that's the size of a thumbnail. In short, that is the challenge semiconductor manufacturers face when producing the most advanced AI chips.   

Production of today's most advanced chips uses a cutting-edge technology called: Extreme Ultraviolet Lithography, or EUV. Listen in as Mr. Toshimichi Iwai, Senior Vice President of E-Beam Lithography at Advantest's R&D facility in Saitama, Japan, explains the history and importance of lithography in semiconductor manufacturing and the vital role that Advantest plays in enabling next-generation semiconductor devices.    

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KEITH SCHAUB: This is Keith Schaub, Vice President of Technology and Strategy, hosting Advantest Talks Semi. We have some important Advantest news from Hira Hassan, our Global Marketing Communications Specialist, followed by some recent event highlights with Junko’s top three. First, we go to Hira for the news. 

KEITH SCHAUB: Hello, Hira 

HIRA HASSAN: Hi Keith, we are so excited to share a number of new exciting products that have been launched this month. Please check out our news page on advantest.com to read more about our product launches. Coming up, we are looking forward to participating in SEMICON Japan in Tokyo, Japan, from December 14th, through the 16th. Make sure to stop by our booth and check out all of our latest advancements and as always, be sure to connect with Advantest on LinkedIn, Twitter, and Facebook for all the news and much more. Junko, on to you. 

JUNKO NAKAYA: Thank you, Hira. My top three in this episode is about ITC International Test Conference, held on October 26th, through 28th at Disneyland Convention Center in Anaheim, California. First, Advantest yet again demonstrated our strong technology leadership, with three technical papers and two poster presentations during ITC. Second, in addition to presentations and posters, we had an interesting product showcase. In the booth, we demonstrated the “R and R” (Repeatability and Reliability) test solution, which was co-developed with STMicroelectronics, and the AOI (Automated Optical Inspection) demo. And, last but not least, it was the first time since the beginning of pandemic for ITC to return as an in-person event, so it was great to have many face to face conversations with our customers, and one of the hot topics seem to be about silent data corruption. That concludes my top three list for ITC. Thanks for listening, and back to you, Keith. 

KEITH SCHAUB: Thank you, Junko, and thank you, Hira, and now onto Advantest Talks Semi. 

KEITH SCHAUB: Nearly everyone is familiar with John F. Kennedy's famous speech. “We choose to go to the moon and to do the other things not because they are easy but because they are hard.” He delivered that speech in September of 1962, but at the time, nobody knew how to land a person on the moon, and many people thought it was impossible. Around that same time, NASA received some strange new “micrologic” chips that were made using a new “shrinking” process called: “lithography,” which ignited the semiconductor industry. The lithography shrinking process has progressed over the years to become one of the most complex processes ever developed. Today, the industry uses Extreme Ultraviolet or EUV, lithographic machines to manufacture the most advanced processors, and there's a saying in the semiconductor industry, “semiconductors aren't rocket science. They're much harder”. It took three decades, billions of dollars, a series of technological mind-boggling innovations, and the creation of one of the world's most complex supply chains to even develop EUV. 

KEITH SCHAUB: Hello and welcome to Advantest Talks Semi. I'm your host, Keith Schaub, Vice President of Technology and Strategy at Advantest. The following are excerpts from a recent conversation I had with Mr. Toshimichi Iwai, Senior Vice President of E-Beam Lithography at Advantest’s R&D facility in Saitama, Japan, where we are talking about the evolution of lithography and semiconductor manufacturing and the important role that Advantest plays in helping to enable next-generation semiconductor chips. 

KEITH SCHAUB: Hi Toshi, Youkoso, Welcome to Advantest Talks Semi. 

TOSHIMICHI IWAI: Thank you for inviting me. 

KEITH SCHAUB: Simple lithography, as I would describe it, is a process where we shine a light source through a photo mask onto a wafer. The mask is a specially designed plate that allows light to shine through it in a tiny, defined pattern. The tiny patterns of light that shine through react with the photoresist chemicals on the wafer, and later, those areas can be etched away. This process is repeated over and over and is similar to building a skyscraper floor by floor. One of the key elements used in the lithography process is the mask. The mask is a sort of blueprint that is used to focus and direct the light into tiny shapes onto the wafer. Maybe you played shadow puppets with small children, or you used your hands to cast an animal shadow like a dog or a rabbit onto the wall. This shadow casting is the same principle used in lithography. In semiconductor lithography, the mask is used to cast a kind of reverse shadow onto the wafer. Here's how Toshi describes it. 

TOSHIMICHI IWAI: Chip has a many, many line space or many shape on the silicon wafer. So, mask is original designing pattern on the mask. So, the lithography tool like a step our scanner expose the mask shape onto the silicon wafer, the pattern size is 1:4. So, if you need 100-nanometer pattern on the silicon wafer four times the bigger pattern on the mask, like 400 nanometer. This is a simple relationship in between silicon and mask itself. So, mask is made by the silicon glass plus silica pattern or chrome pattern to shut the exposure right itself. On the other hand, on the silicon wafer side, it is necessary to resist layer making before the exposing. This is kind of resist react on the light source. If mask cut off the light source on this area, resist will not react, then pattern-making on the silicon. This is a simple phenomenon or simple explanation. 

KEITH SCHAUB: Lithography, innovation, and evolution have undergone multiple phases and continue to this day. In the 1960s, we started with contact printing, but that was soon replaced by proximity printing, proximity printing was good up to two microns but to shrink further. In the 1980s and 90s, the industry developed lithographic projection printing, which opened up the nanometer era. This was later followed by wet immersion then DUV (Deep Ultraviolet) and most recently, EUV (Extreme Ultraviolet). As Toshi described earlier, the lithography process is similar to photography, and our goal is to cast the smallest line width possible onto the wafer. That size, called the critical dimension, or CD, is defined by a very simple formula. CD is equal to K1 times lambda divided by NA. So, there are only three parameters that can be adjusted: K1, constant that can't be smaller than 0.5 lambda, which is the wavelength of the light source; and NA, which stands for Numerical Aperture. To achieve smaller CDs, we need shorter wavelengths, and or we need higher NAs. Listen in as Toshi quickly walks us through to today's state of the art EUV process. 

TOSHIMICHI IWAI: So recently, the chip size is shrinking; therefore, the mask pattern also shrinking. To realize such a scaling, it is necessary to have the optical light source wavelength becomes shorter. So, the g-line, i-line, KrF, and ArF, ArF emersion then now in the moment, EUV light source on the mass production now. So, this is the state-of-the-art chip making process now. 

KEITH SCHAUB: Printing and patterning a chip requires multiple patterns and multiple layers, similar to building a skyscraper floor by floor. Some of today's most advanced chips have 20 plus layers, even as high as 100. 

TOSHIMICHI IWAI: After printing, etching, litho-etch-litho-etch, this is kind of double-patterning. Then after that again the process to another next layer. Again, litho-etch-litho-etch. Most recent high technology chips have more than 20 layers. 

KEITH SCHAUB: DUV, Deep Ultraviolet, is still a big workhorse in the industry today. But to go even smaller, we had to move to EUV, Extreme Ultraviolet. EUV operates at 13.5 nanometers, and it took nearly three decades, billions of dollars, and multiple innovations to finally get there. One of the amazing innovations is with the optics and the mirror technology. 

TOSHIMICHI IWAI: The name itself coming from the wavelength. DUV, Deep Ultraviolet area. EUV is the Extreme Ultraviolet area. So the light source wavelengths of light sources big difference but for the scanner tool point of view or optics point of view there are big changing from DUV to EUV. Up to DUV generations the optics, is simply lens optics lens optics is just lens you have eye-glass, this is also lens, this is lens. But in the case of EUV, very short wavelength area, it is very difficult to make us a normal lens type. So therefore, the EUV scanner have mirror type of lens - parabolic type, so the optic light source is focused on to the silicon wafer side by using a parabolic mirror type, so this is different from that DUV vision. Only one choice to make a mirror type to focus of such a short wavelength. 

KEITH SCHAUB: Building a perfect skyscraper connecting all the layers as perfectly and accurately as possible, is critical. And even though we use the EUV at 13.5 nm, we still want and need to print smaller dimensions. And the industry uses all sorts of tricks to print five nanometers, and even three nanometer sizes is one of the tricks used is Double Patterning. Listen in as Toshi describes how that works. 

TOSHIMICHI IWAI: 13.5 nanometer EPE, Edge Placement Error. This is a key measurement methodology to evaluate the Lithography tool itself or overlay. So, you know that there are many, many, many layers the 100 layers, so each layer exactly aligned to connect layer to layer so, Edge Placement Error is key factor. How good aligned to layer to layer not only layer to layer inside the layer also very important because nowadays, Double Patterning is main lithography process. It means it is necessary to have two times Lithography can have Lithography one time. Then next time making a pattern, something in between by the first shot. So, the optical resolution is limited, 100 nanometer line space lanes. Then this is one - time shot. Then next time shot just shifted 50 nanometers. Again, making 100 nanometer line space. So, after that, actually we have 50 nanometer line space. This is Double Patterning. In this case, if first shot and the second shot would have some misalignment. Therefore, EPE is very important. 

KEITH SCHAUB: Remember we mentioned NA (Numerical Aperture) a bit earlier as one of the parameters that could be adjusted to achieve smaller geometries? Here's how Toshi describes it. 

TOSHIMICHI IWAI: Numerical Aperture, so this is the key number of how to get the high resolutions. Big NA so, this is a lens parameter big NA makes a very high-resolution imaging so, now EUV process, let’s say, something around 0.33. If this 0.33 were doubled, 0.66 the resolution becomes half, this is the relationship. This is totally optical designing very very complicated to the lens type lens shape optical path and many factor including this works done by Carl Zeiss in Germany Carl Zeiss is a partner of ASML. All of the ASML tool optical design is done by Carl Zeiss. They have unique technology so-called Anamorphic Optics so, it is very difficult to achieve the high NA increase for all of the view. Light source is normally exactly circle. In this case NA is exactly the same everywhere, but for making a high NA by using the parabolic mirror, there are some limitation to making a high NA optics. So Carl Zeiss and ASML decided to have a asymmetric light source shape - anamorphic. So, in this case, the NA is not exactly the same, so this is quite complicated. The designing change for the chip making especially for mask design. 

KEITH SCHAUB: Today we can print five nanometers and even three nanometers. What about two nanometers and beyond? 

TOSHIMICHI IWAI: Beyond two nanometer, nobody knows what will be happened. This is totally physics. You know transistor how transistor works this is very deeply physics concerned. If the transistor size becomes small, small, small, transistor type designers should discuss tunneling effect. They are thinking about atomic-level control. All of the process tools, including the methodology tool. 

KEITH SCHAUB: There are new optics being invented and developed for next-generation systems. The way we design new masks is completely changing. Geometric shapes can now interfere with one another and must be well understood and modeled, and there are some important measurements that help us measure and control these shapes, such as OPC (Optical Proximity Correction) and CDU (Critical Dimension Uniformity). 

TOSHIMICHI IWAI: So, for the optics theory, it is necessary to have some type of correction pattern. That it means the shape on the silicon and the shape on the mask is not the exactly same based upon the optics. There are some type of the optics error factor including how to correct such optics error. The mask designer calls it "Optical Proximity Correction." OPC so, OPC pattern is very unique and very complicated. Methodology tool should control how good OPC shape already making or shape is some error including not only smallest pattern, but also two dimensional imaging evaluation is key factor for the EUV generation. But nowadays there are many, many unique patterns on the mask. Therefore, it is necessary to measure two-dimensional pattern shape itself not only pattern width. So, this is the recent methodology topics. For example, for the one-dimensional measurement accuracy is below 0.1 nanometers three sigma this is atomic level. For the mask point of view, they have specification like CDU CD uniformity, CD is Critical Dimension, and uniformity all over the mask so, Lithography team request for mask team should have one nanometer uniformity mask all over the mask area. So, mask uniformity specifications, let's say about one nanometer for EUV mask. Therefore, metrology tool should control to accuracy less than 0.1 nanometer. 

KEITH SCHAUB: Although EUV technology is finally available, EUV is still relatively new, and it isn't without some major challenges that Advantest is helping to resolve. 

TOSHIMICHI IWAI: E5620, this is a mask review SEM (Scanning Electron Microscope). This is review tool dedicated to the EUV mask. I need to explain another story of the EUV mask. Smart phone, your smart phone have to protect glass film to protect your display all over the mask should have protecting material for the mask surface because if tiny dust dropped onto the mask surface, the productivity or yield of the silicon wafer will drastically dropped down. So, EUV light source is still very low, 1/10th the power of DUV. So, if EUV mask would have some specific cover, it means the light source power is further reduced something around 20% or 30%. This is (too much power loss) direct impact to the productivity or throughput. So therefore, nowadays, EUV masks do not use any dust protecting cover. It means it is necessary to frequently check (validate and verify the cleanliness of the MASK) how this EUV mask still keep clean or are there some contamination on the mask surface. So, Lithography team keep watching the yield. If (yield) starting to drop down, where is a dust, where is a contamination? What happened on the mask surface? This should be done by laser tech tool. This is the main reason why the laser tech company is booming up in the in the silicon market here in Japan, but unfortunately laser tech tool can indicate where is the dust is but cannot indicate what is the dust material itself and exact size of the particle itself because of the resolution limitations. Our product, E5610 MASK review SEM, is high resolution plus we have this tool has EDX analyzer, this is composite analyzer by X ray so, 10 kV electron beam energy hit on the mask surface, it becomes X ray producing, then the analyzing the X ray, it is possible to know what is the material is. So, many (our Advantest) E5610 is working just below the ASML EUV scanner tool or E5620 next generation mask DR-SEM is we achieved completely fully automation and high throughput. So, this is our product that we are (debuting) at SEMICON Japan. 

KEITH SCHAUB: What's next? ASML, IMEC, and Advantest are collaborating on next-generation chip manufacturing technology. IMEC is well known for its expertise in shrinking circuitry for nanotechnology industries. In 2015, the New York Times stated that IMEC, has helped pioneer techniques to produce some of the world's smallest and most sophisticated chips and is considered to be a world leader in nanoelectronics research. Listen in as Toshi describes the collaboration and where the industry is headed. 

TOSHIMICHI IWAI: For the chip shrinkage or scaling, it is necessary to have more high-resolution tool EUV scanner. So, next generation EUV scanner high NA type not only (the) silicon wafer process but also mask making process (is going through some dramatic changes), because of the anamorphic optical design. IMEC is worldwide (leader in semiconductor nanotechnology). IMEC and ASML just started some collaboration work for the high NA level. So beta-level high NA tool start to fabrication in Netherlands and ASML facilities. So, they have that collaborated each other to evaluate all of the total process by using the high NA EUV Lithography. Lithography, process done by ASML (in) the Netherlands. Then wafer moves to the IMEC (in Belgium). Then in IMEC, the silicon wafer (undergoes) another process and evaluation. And ASML and IMEC decided to (combine) the mask evaluation too because of the mask design also (undergoing) big changing. So, main topics of this evaluation is kind of print-ability, so that shape on the silicon wafer and shape on the mask has big changing. So, they should check print-ability - how exact printed result on the silicon wafer. For this purpose, it is necessary to measure the shape on the mask and the measure (the shape) on the silicon too and to compare what this happened. So, we (Advantest) decided to join this high NA evaluation by using our state of the art mask CD-SEM E3650, and IMEC already selected our tool and just started installation in this month. And also, we have the sign off of the joint development agreement between IMEC and Advantest (of) how to evaluate the mask high NA EUV mask. So, it will be take two or three years for this program. We should know what the key point of the mask methodology is especially for high NA EUV mask type. Then we should keep very specific algorithm into our tool. Then our tool should be the de facto standard to all the high NA EUV tool. This is our strategy for the next generation. 

KEITH SCHAUB: Toshi, we are nearing the end of the show. What final thoughts would you like to leave with us? 

TOSHIMICHI IWAI: Yeah, nobody knows how to how to evaluate the high NA mask (by) working with (both) IMEC and ASML, we should know: What is the key point for the mask methodology? What is the impact to silicon wafer print-ability, and what is the necessary shape of the Optical Proximity Correction – OPC. (From the collaboration with IMEC, we expect) many fruitful knowledge. 

KEITH SCHAUB: Thank you, Toshi. Again, it was wonderful to talk to you today and thank you for taking the time to educate us on the fascinating world of nanotechnology and how the semiconductor industry manufacturers chips, and most importantly, how Advantest technology is used throughout the process and across the industry. 

TOSHIMICHI IWAI: You are welcome. Thank you, Keith. 

KEITH SCHAUB: Well, that does it for this episode of Advantest Talks Semi. See you next time.