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Advantest Talks Semi
Dive into the world of semiconductors and Automatic Test Equipment with our educational podcast, Advantest Talks Semi, where we explore the power of knowledge in this dynamic field. Hosted by Keith Schaub, Vice President of Technology and Strategy and Don Ong, Director and Head of Innovation for Advantest Field Service Business Group, at Advantest, this series features insightful conversations with experts and thought leaders in the industry.
In today's fast-paced environment, continuous learning is essential for staying ahead. Join us in these thought-provoking discussions, where you can learn about the latest trends and cutting-edge strategies being used in the semiconductor industry. Explore how innovative technologies are revolutionizing testing processes and shaping the future.
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Advantest Talks Semi
Probing the Future with FormFactor
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Hello and welcome to Advanced Test Talk Simi. Today I'm your host, Keith Schaub, and we're zooming in on the last few millimeters between silicon and certainty, the probe card. My guest is Acatosh Deve, Chief Commercial Officer at Form Factor. Acetosh brings more than two decades of semiconductor know-how from process engineering at AMD to nine years leading global metrology inspection at ASML before taking the commercial helm at Form Factor in 2024. So Form Factor itself began life in 1993 when a tiny New York lab turned a micro spring epiphany into a new class of probe technology. Here we are, three decades later, and the company is the world's number one supplier of advanced probe cards and engineering probe stations, having shipped over 115 million MIMS probes every year to fabs tackling everything from HBM stacks to quantum qubits. So in the next hour, we're going to unpack this journey. We're going to explore the toughest probing challenges ahead, and we're going to hear how Form Factor is keeping electrical integrity intact at 112 gigabits per second at minus 40 degrees Celsius. So grab your coffee and your curiosity. This is going to be a masterclass in the art and science of first contact. Okay, so Achitosh, welcome to Advanced Test Talk Simi.
SPEAKER_03:Thanks a lot, Keith. I'm actually very privileged and I'm honored to be over here on the host uh on the uh talk show along with you. A little bit about myself. I grew up in India. I started my career as an RD uh litho process engineer. So I was a metal implant layer owner. So I was working on those, and then what happened is AMD expansion split. And now you're a process engineer working in the clean room and you don't have a fab. What do you do? So then uh eventually what happened is I moved on to uh more onto the computational lithography side, more onto the software side, call it optical proximity correction. Then I transitioned from clean room to more onto the desk. There was a time when I moved uh from uh AMD to a company called Mentographics. Uh so they were a supplier who was providing solutions on uh this uh resolution enhancement techniques and optical proximity corrections. So more onto the design side. And that's where when I transitioned from hardcore RD to more onto technical marketing. Eventually I moved on to sales and business development. So I've done front-end uh process, I've done uh front-end design, I got very familiar with uh not just the back-end design aspect, but also the front-end design aspect because now you're talking about this entire design from manufacturability, DFM, place and route, everything. I was with Mentigraphics for about eight years and then I transitioned uh to ASML. I got uh more into the actual core lithography area. That is when I got introduced to back-end testing measurement, actually, because so many times on the inspection side, you still want to see whether the defects are real or not. And that's where the probe really comes into the picture. And I knew Mike Slesser, uh, so that is when he asked if I would be interested in joining Fun Factor. And that's my journey.
SPEAKER_00:Yeah, we're happy to have you. We've been collaborating in in uh certain spaces like Silicon Photonics, which we'll get into later. We're actually on two opposite sides of the same coin because you spent most of your career in the front end, and I've spent most of mine, almost all of my career in the back end. And it would be interesting to hear your now that you're on the the the better side, let's say. So you've joined the better side, it would be interesting to hear how you see that landscape has changed and the differences between what's going on in the front end and the maturity levels and how that's different with with the back end.
SPEAKER_03:So yeah, so let me begin. I I I don't think it is uh two different sides, right? Uh I would still say it uh that we are all serving the semiconductor ecosystem widely as we as we evolve all these uh product and technology uh in the industry overall. I would say uh front end uh you know it has its own challenges. It was one of the driving factors of uh the device technology and the growth that we have seen in the semiconductor industry for many years, whereas uh the back end was more as a, you know, as a commodity market uh for many years. And what is happening is if you start looking at uh where the industry is headed, you know, we we have our own challenges uh driving down technology from you know many generations down to 10, uh, seven, five, four, three. And now we are talking about angstrom level. So front end still has its own challenges, and and there are companies which are working hard on that. But what is also happening is the back end, which uh now we start seeing all these uh yield challenges, the known good dyes become a lot more critical. And the cost of uh test and measurement uh for not uh basically letting go some of these uh bad dyes, the cost is becoming a quite significant factor, which uh what customers want is they want to solve these issues. And this is where the test and measurement now is becoming I don't want to say a bottleneck, but one of the areas of focus to ensure that uh there are better known good dyes and uh overall we can produce uh more reliable and high quality product that goes into the end consumers.
SPEAKER_00:Yeah. So you mentioned the migration or the the value shift from commodity to enablement, where we're also as advantage, a semiconductor test supplier, uh, we view ourselves and most of our customers now view us as a technology enabler, and it's an essential part of the ecosystem. Let's look at that in terms of the markets and technology for a moment. So form factor, you guys obviously make probe cards who address probe challenges primarily at wafer, but for all sorts of different technology uh slices. So you have logic, you have memory, you have RF, sort of walk through what are those different technology how slices, how do you guys slice it up? Yeah. Then what are some of the major challenges that you see from one to the other, or are they all very similar?
SPEAKER_03:No, th they're very different, actually. And and you bring a good point, right? So if you look at uh this entire semiconductor ecosystem, and if you break it down by market segment, right, each uh segment has their has their own challenges, right? So what I was talking about uh back in touch and measurement becoming mainframe, where it needs uh own development and and more emphasis in terms of what concerns uh are there in terms of the yield and known good dies, break it out into different segments, right? You you look at logic, so c devices, uh one segment, uh, memory, and even in memory, then you split it up between uh DRAM, uh, NAND, NOR. But more important, what is happening is with the AI inflection, um, basically we are seeing quite some challenges on the HBM, high bandwidth memory. So that has its own requirements. And you then also look at the other sectors like you know, auto industry, you look at uh RF market, you look at uh, you know, the mobile. So there are many different segments, and each of these segments uh the technology is becoming challenging. Uh, back in testion measurement has its own requirements for each of these areas, and that's where we are focused on. So if you look at uh form factor, we are the only company that provides and serves uh this entire spectrum uh of industry today.
SPEAKER_00:Interesting. So all these different segments, same for advan test, we have different modules and different tester capabilities that serve different markets. Since obviously AI and HBM is sort of the hot topic in the global industry today, maybe let's focus in on that one and talk about what the probe technology looks like and the challenges for that specific market. I I think I remember reading uh Form Factor recently won um best supplier award from SK Heinex and maybe something from Tech Insights. Can can you talk about that a little bit?
SPEAKER_03:Sure. So let me segue this into different areas, right? So Form Factor has been uh number one uh Probe Cut supplier today. Um and we do win a lot of uploads uh from customers like you know, Heinex. We won um, we basically got the number one supplier award. We get similar from other customers too. Uh not only that, recently we also got awarded as the number one supplier in the sector from Tech Insights. So it's not just from uh the technology that we get testament and basically awards from the customers, uh, but we also get more from customer satisfaction point of view, right? So it's not just technology, but it's also how you support the customers. And there's a lot, there, there's a lot of work that goes behind getting these awards, right? As you can imagine. And this is uh the work that we put in over the years, right? So over the years, what has happened is there are many challenges. You talked about AI, you talked about uh uh HBM, right? If you focus on that for memory applications, and especially for high-bandwidth memory applications, um, we have solutions uh that uh basically we call it smart matrix products. Uh so that kind of product is needed for when you start talking about HBM, the bandwidth requirements, the requirements that uh, you know, you're talking about stack die, you're talking about uh base die, core die. But more also important, uh, even having uh, you know, known good dyes at wafer level. Can you do one touchdown solution versus uh what are the lifespan of these uh probe cards? But if you get into more technical details, the more technical details are how do you have a reliable solution that gives you the basically what we call, you know, we measure in terms of uh current carrying capabilities or force and the pitch requirements, but there are many more details that are required from each probe cards and the technology that goes behind it. And we have been working very closely with the customers to make sure we have solutions uh that uh resolve the challenges that customers are facing today.
SPEAKER_00:Okay, so you mentioned pitch for the audience that may not know what pitch is. Yeah. Let's talk a little bit about the AI chips and how they're growing massively. Yeah. And I think what's happening is uh as they get larger, the probe contact points uh grow.
SPEAKER_01:Yeah.
SPEAKER_00:And there's you start running out of space. Yes. So you have to now shrink the distance between the the pads. Can you talk about like where where are we at in the industry with that and how do we solve that problem?
SPEAKER_03:Sure. Yeah, so so it's uh it's also quite interesting and funny in a way that when I when I joined from ESML, you know, you talk about nanometers and angstroms, and you come onto the backend uh test and measurement side and you start talking about microns, right? So what is really happening is if you look at the overall uh semiconductor devices, right? And I'm not gonna pick a particular one in terms of logic or memory, but in general, there's device scaling. So when you do device scaling, you're shrinking the device to have more transistors uh per chip, right? To have more memory per chip. So you look at historic, uh, you know, having a memory uh chiplet which would have uh, you know, 64 gigabytes and it'll be quite huge uh chiplet. Now, the same thing, you can get it in like uh, you know, pretty small uh chiplet, the same uh size of uh memory. So overall device scaling is driving the density uh much more tighter. That poses a risk on the test and measurement side too. So as you shrink the devices to get more transistors, more juice out of the same chip, making things smaller, talking about the Moore's law and everything. So, following that, the back in the test and measurement side, what was interesting is we had the leverage of having a particular patch size where you do the probe testing. And the pad sizes were you know big enough, but now as you scale the devices small, it's not just the pitch that is scaling, it's also the pad sizes that are getting smaller.
SPEAKER_00:I see.
SPEAKER_03:So so this is one of the requirements that uh the customers are pushing us, and this is also where form factor is focusing on is to say, how are we gonna scale? What is uh the minimum pitch uh that we can support in terms of uh probing and not just the minimum pitch of these probes, but also you have to be exactly in the center of the pad to make sure that you have better contact resistance.
SPEAKER_01:Yeah.
SPEAKER_03:So so both of these requirements are needed uh when you're talking about just the pitch scaling.
SPEAKER_00:So let's put that into perspective because uh I want to make sure the audience understands the enormity of the challenge and that we're not talking about a few hundred pins here, we're talking about thousands and thousands of pins. I mean, how how do you do that and have it plainer? Yeah. And then how do you even like what what happens when something breaks and you need to repair it?
SPEAKER_03:Yeah, so so uh yeah, the the it like like I said, right? Like the industry is shifting more on to doing more and more tests now.
SPEAKER_01:Right.
SPEAKER_03:Right. The risk of not having known good dies is quite enormous. So and not just uh it's non-good dyes, but it's it's also the test and measurement requirement is growing because now customers want to test uh different parameters, they want to test a lot more. So, what is also uh happening is uh you need to have more pin counts. That's number one. But the second thing is also as you start scaling and you start doing more parallelism, uh, there are more pin counts that are required.
SPEAKER_00:And um, and that's to reduce drive the cost down because you can do more in parallel, basically. Absolutely. So that's one of the best ways to drive and scale down the costs.
SPEAKER_03:And and this is where it's also interesting is uh you you you have different requirements for memory versus uh logic SOC applications, and and on the memory application side, the test requirements are different. So there you're talking about uh maybe um you you're still talking about wafer level, but you're talking about multiple dice together. So you're talking about 100,000 pins or more. Oh wow. But you're doing multiple dice together. Uh the test requirements are different. Customers push us into one touchdown solutions. And yes, it's not no longer a few hundred pins. Uh, you're talking about a hundred thousand and more pins, right? On the the logic SOC, it's it's also quite different now compared to memory, but there you have uh the test requirements are very different because you need different kinds of parametric testing for the logic socces. So you're still talking about one die, a single-led die, which will need uh you know, a few tens of thousands of pin. So, in order to reduce cost, like you said, uh you have to do multi-sites. And when you start doing multi-sites, that is where you are talking about uh reducing cost by adding more sites to it. But the complexity in terms of this entire interface with the PCB and then the test uh programs that you have, you're talking about uh, you know, by four, by ten, by sixteen, uh, depending upon the test complexity and how much parallelism can we do.
SPEAKER_00:First of all, I I still can't wrap my head around a hundred thousand pens somehow being coplanar. Yeah. But you obviously do that. So congratulations. I don't know how you do that, but that's that's amazing. Yeah. Uh we were talking before the show about when I first started, I was doing on wafer probe testing using RF probes uh from Cascade, which got acquired uh by uh Form Factor, I believe, in 2016 or 2012, something like that. And those probes at that time, they they were like angled and they would scrape to like bust the oxide and scrape onto the device.
SPEAKER_01:Yeah.
SPEAKER_00:But I'm assuming now, I mean, with a hundred thousand pins, you can't do that anymore. So how how do you how do you resolve that?
SPEAKER_03:Yeah, so this is uh like uh like I was talking about, uh, you know, form factor has a huge spectrum of applications. And if you look at uh the industry today, especially on the memory HBM applications, uh we have a uh product uh called Smart Matrix. So we they are the 3D MEMPS probes. And the requirements in terms of uh the bandwidth, the requirements in terms of the space uh you're talking about, it's very different. And the specification that uh you need for HBM applications, we have pioneered that. And that is very different than the logic SOC applications where you have vertical probes. And because uh on the SOC side, your current requirements are different compared to the force requirements and the bandwidth requirements, the materials are different. And we do have many of these different probe types uh that serve uh the segment market.
SPEAKER_00:I see. Well, we do now have these vertical pins that for I guess the easiest way to think about it, a bed of nails almost, it just comes straight down and makes contact, and you have thousands and thousands of those. Yeah.
SPEAKER_03:Uh smaller than a hair?
SPEAKER_00:Yeah. Smaller than a hair. That's amazing. So do you do that also for stack dye? So that's the the the pins are at different coplanar levels?
SPEAKER_03:So for stack die, uh again, uh we we you know, on the memory application side, you do uh wafer level tests, you do singulated dye tests, you do stack dye tests. So there are many different applications. On the SOC side and the advanced packaging side, yes, there are hybrid probing requirements that will need different kinds of probes on the same uh probe card. One thing I wanted to add is uh you you asked about vertical and the 3D probes.
SPEAKER_01:Yeah.
SPEAKER_03:You know, customers ask, hey, can we use vertical probe for memory devices or can you use vertical probes for RF devices, right? So on RF we have we call it P probes on flexible substrates. The requirements and the test measurements are very different. It's not that you cannot do it. Absolutely, you can use the same probe at many different places because at the end of the day you need contact. But the test complexity is so different that uh you do need to optimize the tests, uh, the materials, the spring type we call 3D, 2D, flexible for those applications. And that is where we have been spending a lot of time in uh you know RD to say, okay, what probe type is the best for customer applications?
SPEAKER_00:I see. Yeah, that makes a lot of sense. Let's take a small tangent and talk about form factors history. Can you walk us through? I mean, what were the inflections or what was going on in the market to uh um to have those acquisitions? I mean, was there some new technology that was required or what was happening in the market to make it?
SPEAKER_03:Yeah, so uh I'll I'll try to do as much as I can. As you know, I've been with Form Factor now about a year and a half, right? Uh, but uh if you look at the history, right, it's not just a form factor history. If you look at the entire test and measurement industry, right, over the last uh 20, 30 years, there was a lot of uh consolidation, mergers, and acquisitions um over the years. And form factor has been there for a very long time. And some of these acquisitions, like the microprobe, they had a solution more onto the memory application versus form factor was pioneered in logic applications. So that is a good uh uh you know collaboration where uh form factor acquired microprobe and now Mike Slister or CEO, he he came from microprobe, actually. But all of this is, you know, in parallel to what is needed in the semiconductor industry from back intestine measurement side. You you have to notice that similar kind of things also happen on the customer side. There's a lot of mergers, consolidation. It also happened in the front end side. Yeah, you see that happening on the back end side now.
SPEAKER_01:Yeah.
SPEAKER_03:Uh and and over the years, uh Advantis did something similar, right? Uh they have acquired so many companies in the past. As the requirements are getting more complex, there's more need for collaboration. There's more need for kind of mergers, acquisitions in a way, you may call it, or you know, partnership in the industry.
SPEAKER_00:Yeah, I want to key off of your collaboration there. So one of the things we've heard in industry that's I think resonating with everyone is that the complexity of producing semiconductors is so great now that there's no way to bring these products to market without very strong collaboration, even sometimes between competitors. Yes. We see that a lot. Obviously, we have uh some partnership uh projects with form factor, especially with with silicon photonics, yeah, and how the market is changing and customers' demand for us to do things and some of it we can't do. And I'm sure customers demand you guys to do things, and some of that you can't do. So we're by necessity, we have to collaborate. So let's talk a little bit about what sort of collaborations you see, not just maybe with that advanced, but with use that you see with with customers or with partners in general.
SPEAKER_03:Take a step back. We talked about microprobe and pump factor. Casket is uh is also interesting. So form factor, what we provide is we provide from lab to fab solution. So we do um uh test systems, uh early RD lab environment where we uh have test systems that measure from uh you know RFDC applications. Uh we have we have been in silicon photonics for quite some years now. And then connecting back to applications onto the HVM side where the probe cards are uh into more HVM environment. And we also have quantum cryogenic solutions where we look at uh cryogenic uh, you know, it's also on the lab side today, but there are features and functionalities on the thermal side which are needed on the probe card side, for example. So this is where uh, you know, even within Form Factor, we do have an ecosystem to go from lab to fab. Now, if you connect that with the outside world, we also look at uh collaboration uh areas on the vertical segment side. So Form Factor has always believed in open ecosystem, and similar to Advantus, actually, I appreciate and admire the fact that Advantas invested uh part of it in uh Form Factor earlier this year. And uh similarly, uh you do it with other partners because this is what the customers really require. And they want an open ecosystem where we can give the best solutions to the customer, but it also fosters code development. It also fosters code development in a way that will kind of you know expedite some of these roadmaps rather than doing it by yourself. You're collaborating and partnering and getting the solutions to the customers much faster. So Form Factor has uh has also invested in FICT, which is uh more onto the substrate MLO side to make sure that we similarly on uh how we work with Advantage, we work with uh the vertical uh suppliers too. So so that's uh that is what is going on. Now, switch gears to silicon photonics. This is one area where form factor has been in the market for a long time. Uh, we have shipped more than hundreds of systems of silicon photonics in the past. Uh we have those application layers, and there is a need now, we are at uh this industry inflection point, right? Uh where there's need for HVM solution. So, this is where we partner with Advantas because you are the pioneer and uh leader in ATE uh for HVM requirements.
SPEAKER_00:So let's talk about that silicon photonics a little bit more. So, first of all, just to sort of set this up. Jensen recently gave his keynote and he sh he showed the amount of copper in the backbone and how many miles of copper it is, or I don't know, it weighed 2,000 tons. Yeah. And the nuclear reactors needed. Yeah, and and the amount of energy that's required in the data centers that are being built and the energy that's required to uh supply those data centers is largely because we're just moving data around. We're moving data from the CPU or GPU to memory and then back and forth. And so now there's this, as you as you alluded to, there's this emerging silicon photonics where we could move the data optically, which dramatically reduces uh the energy. Sounds great, but it introduces a whole new set of test challenges because the interfacing and the form factor Pun intended, the form factor is completely different. Yes. So talk to me a little bit about like w what is actually changing and and what are the the challenges associated with with addressing silicon batonics and co-packaged optics.
SPEAKER_03:Yeah, so so if you take a step back, right, uh if you look at the data bandwidth requirement from test point of view, uh you cannot do it just by electric alone, right? You you need uh optical and electrical I/O. And that is what Jensen was mentioning in the GTC, that if you look at uh industry, the optical I.O. is needed for AI and uh hyperscalers. Um so the industry is already talking about you, you are you hear about Epic, you hear about uh CPO, co-packaged uh optics. And uh it's the silicon photonics is not new. It's been there in the in the in the industry for a long time. As a matter of fact, I was listening to one of the podcasts uh you had before with Dr. uh Bailey. To me, it it's been there. It's just like making sure that if you look at this inflection point in the industry, the need is today to say how do we really leverage having both uh electronics and optics together on the same chip versus start testing it because the the need from the data centers, the need from the AI, everything is there. Now, it's easy said than done. The requirements are very different, right? Yeah, and and now you're talking about uh measuring uh you know optical uh chiplets and measuring electrical chiplets and uh combined along with that one's packaging. So this is uh where the industry is headed. It's not if and ha, it's not about um are we going are they going to do it or not? It's timing.
SPEAKER_01:Yeah.
SPEAKER_03:And the timing is now. So many of these customers are requesting and are requesting at a much expedited level to say, when can you deliver silicon photonic solution for HVM today, right? And and how fast can we do it? Now, what is happening is it's interesting. Uh, you know, I hear this term called um you're you're building a bridge while you're crossing it.
SPEAKER_00:Yes. Uh building the plane while you're flying it.
SPEAKER_03:That sounds scary. Very dangerous. But uh that is uh actually what is happening on the silicon photonic side is the industry is kind of streamlining and standardizing the test requirements, but at the same time, uh the suppliers also have to provide solutions. And that is where more collaboration is needed. That is where more understanding about the entire ecosystem, the requirements, not just from the end customer, but even the foundry partners. Uh so this is where Form Factor has been leading, working closely with Advantage and other suppliers and also the customers. What is happening is you mentioned about uh electronics and optics, and this is where we do hybrid uh testing. So we have, like I said, the silicon photonic solution where we measure optical uh signals, but along with the probe card in uh ATEs, we can also do. Uh electrical test. And and this is where the cool package uh testing uh comes in.
SPEAKER_00:And just to key in on one thing you said, silicon photonics isn't new. In fact, I was working on it back in 2007. Yeah. And we had working solutions. We even built modules to test optical parameters, but it never went to HVM. Yeah. So that's the difference where we are now is now there's because of AI, there's an HVM need for silicon photonics and co-packaged optics. It's not of, well, it's a nicety and let's still do research. Yeah. It's now how do we integrate this in a cost-effective way into the entire solution, which then forces us to figure out how to test it.
SPEAKER_03:Absolutely. Absolutely. So it's no longer a transceivers or it it has to be integrated along with all these complex chiplets that we are talking about.
SPEAKER_00:I'm just thinking about what Jensen sh talked about, but also we had AMD at our keynote, and they also showed how this is a necessity now. It's an absolute requirement. And the signal integrity, being able to bring optical signals in and out and have that get connected in some sort of economical HVM way. Yeah. That is extremely challenging. And that was one of the biggest challenges we had back in 2007 is how do you get this fiber cable to line up and meet with some little interface uh on the chip. And of course you can do it, but it's very expensive. Yes. And the challenge is you need to do that in a less expensive, much less expensive way that can have a lifetime in production, not just in the lab. Yes. Because we were doing a lot of that in the lab. So I'm I'm thinking that this is this is going to be uh one of the major, maybe I'm over speaking here, but I think it might be one of the major growth areas or form factor, because it has to be done, or a lot of that has to be done on the probe card itself.
SPEAKER_03:Yes. So so you you you bring a you bring a good point, Keith. So if you look at the challenges that we have at Silicon Photonics today, right? Uh I'm not going to name the customer, but you list the challenges. The challenges are how can you uh correctly align the optical signals, signal integrity, right? Or fidelity that you talk about on the optical side? The noise, actually, uh the vibration and the noise. The fourth thing that uh we talk about is basically uh the time to align, the time to measure, uh calibrate, and measure. And interesting enough, the customer says HVM tools. How quickly can we ramp HVM tools? Because if you are in the lab environment, how many tools do you need? Versus uh the HVM requirements are very different today. We talk about test insertion one, two, like uh some customers say test insertion two, one, it's it's kind of muffled in a way. But those are the requirements from more uh silicon photonics uh today, along with electrical testing, right? The next generation that you're talking about is to have everything on single probe card. That is something that uh yeah, we continue to look into the roadmap uh to say, because today you're still talking about having silicon photonics application layer and uh hybrid uh electric probe card. So you can test both of them. But now can you combine it into a single probe card, for example? Right. Right. So those are more hybrid solutions uh that we have to look into the future roadmap, uh collaborating with partners and suppliers.
SPEAKER_00:Speaking of collaborating with partners and suppliers, I mean, this strikes me as it's pretty cutting-edge technology. Yeah. So but test, as you mentioned earlier, it's often well, it still is, but it's very cost sensitive. So we tend to do cost in areas of the world that are, let's say, somewhat geopolitically unstable. So how do you deal with, you know, you're sending this complex piece of technology, you have to service and maintain it, but it's in a different part of the world. It's probably not so easy to even anyway. How do you do that?
SPEAKER_03:So let me wrap up on the silicon photonics and I'll talk about the cost. So so when I was talking about, you know, building the bridge while you're walking, that is true, because on silicon photonics, you're talking about uh different test insertions on how you're developing a solution, but uh it also depends on the end uh customer, the end design customers. Are they developing the chiplet into the same uh uh way? Are they going to have advanced package, which might be a different direction? So that might have requirements that change. And it becomes important uh for companies like Form Factor, for companies like Advantage to quickly adapt to it and for its solution that is not easy and definitely not cost insensitive in a way, right? But the the next question is that once you start supplying to these customers, and it's not just on the silicon photonic side, more on to the probe card applications too, what is happening is yes, you're absolutely right. Test is it has always been so much cost tringent. And I've worked uh with many customers and many buyers. Uh and what happens is when you're on the front end side, if you say, hey, I need uh, you know, a few hundred million, it's easy to get it. But the same question you ask on the back end side, hey, can I get 10 million? And then uh you basically don't get the CapEx approved, right? So so uh back intestine measurement has always been uh overlooked in the past. The complexity has been overlooked in the past, but things are changing now. So as uh the requirements increase, there's more cost pressure to the customers too. But it's also emphasis to say how do they balance it? Now, that's on one side, but the second side is that pressure is still there. How do we manage and support it? So customers are kind of you know migrating to lower cost region areas, or maybe they will have OSAT partners, which are in some region somewhere. And uh in probe card industry, uh, you have to manage and service these cards similar to how the ATE service uh requirements work. So we have to manage that working closely with the customer, but at least understand uh customer roadmaps. This is also driven by geopolitical uh situations that many governments are investing in the semiconductor space right now. There are fabs and there are OSAT and there are test and measurement uh facilities uh popping up in many countries uh which did not have anything before. How do you create a service uh structure uh that's gonna support these customers? So those are the kind of challenges on the service side, which does impact cost to the customer, but also cost to us. And at Form Factor, we look at this and we uh we work closely with the customers to really understand strategically how to uh have locations so that we can still have faster turnaround time. Because at the end of the day, that is money. If you have wafer sitting not getting tested, that is cost to the customer and it's uh impact of money to the customer. So we have quite a bit of requirements to say service within 24 hours, 48 hours. And what we have done is we have strategically located these service centers uh across uh the world. We as a matter of fact, we look at the volume and we have just doubled our Taiwan service center capacity uh to support uh service and operations requirement in Taiwan, for example.
SPEAKER_00:Not to get too far off in the weeds, but it's often overlooked how important just service and support part of that business is to our customers. I mean, the technology is great. Everyone wants to talk about technology. HVM is all about uptime, reliability, and cost. Yeah. And things break.
unknown:Yeah.
SPEAKER_00:And you need to do that in the most reliable, least costly way uh possible.
SPEAKER_03:Absolutely.
SPEAKER_00:That's a whole nother ecosystem. Probably do a podcast just on that. In terms of the the maintenance, the cleaning, I would imagine that there's a good opportunity to use maybe some some AI technology there to help decide when the cards need to be cleaned or refurbished or repaired. Do you have anything like that?
SPEAKER_03:So it it's a it's an interesting thing. Uh I get uh I get asked this question so many times, like uh how much AI are we really using uh on the service side, for example? Can we predict which pins are going to fail? Um it's very difficult. It's very difficult because when we manufacture probe cards, they're very much design specific. And each design will have different test requirements. However, over the years, there's a lot of knowledge and know-how on how you service these cards for longevity, right? So when we sell probe cards, we customers will expect a uh how many touchdowns you're gonna have. So we talk about the lifespan of probe cards in terms of okay, million touchdowns, two million touchdowns. And what does it take to have those million or two million touchdowns? So regular servicing, making sure that if there are any damaged pins, then we have the capability to fix those things at uh the customer side. And it is complex. It is uh, you know, sometimes you uh we we do this experiment actually. We ask customers to come to the service center and try to take a pin and then put it back in the guide plate. And it does take efforts, right? Um so when it is onesie, two Z pins, you can do it manually. But the moment you talk about multiple pins, then uh there are tools which can do it. So so the overall turnaround time is still much faster.
SPEAKER_00:I I can imagine that again, that would be an entire could be an entire ecosystem unto itself. That actually brings me to a new part of the podcast I want to uh try out with you today. Sure. So I did an experiment with ChatGPT, the latest and greatest model, uh, or one of the greatest, latest models, a 3-0 model. And I basically asked the question to speculate on what sort of innovations could happen with probe card technology over the next five years. And it came up with uh some, I don't know, maybe plausible or science fiction uh ideas. And I thought I would throw these out at you and you should could could give some uh commentary on uh that's all science fiction, or uh maybe some of that's plausible. We can call this pin count prophecies.
SPEAKER_01:Okay.
SPEAKER_00:All right. So these are bold predictions by GP303. The idea was to get down to sub-15 micron verticals, uh, but to do that, um reduce the force by using electrostatic zero forcing. You have all these pins, uh, they're pretty close, and create this electrostatic hole that you could get rid of the or at least eliminate the force challenge that I'm I'm sure is a considerable challenge when you're trying to connect a hundred thousand pins down onto a wafer. So so what do you think about that? That would eliminate the scrub entirely, yeah. And it would be perfect for bumpless backside power wafer testing. Absolutely. So is it science fiction or is that possible?
SPEAKER_03:Wow. So I'm not a technology expert. Uh I was thinking, should I wear my meta glasses and ask uh Meta AI? But uh no, Keith, uh this is uh actually it is not completely science fiction either, right? If you look at uh where the industry is headed, the pitch scaling, the the pads scaling. So the sub uh you you talked about sub-15 microns. Uh maybe it's still further out in the roadmap, but yes, customers are hard driving, uh the pitch down, the bump sizes are reducing, right? And the other thing that uh we did not touch base earlier is uh the g force, right? So when we talk about touching uh the approach touching the vapor, the materials are also getting sensitive to say, what kind of scrub mark do you want? At the end of the day, you want to make sure that you have good contact resistance. And um how much force do you apply? How much overdrive do you do? So, yeah, all of that is good, but the electrostatic uh zero g force, I don't know about that, right? That's uh that's a far-fetched out.
SPEAKER_00:Maybe 20 2035. Yeah. Okay, so the next one was uh the matrix X contactor. So you mentioned something about matrix solutions that you have already, and I guess it took it to the extreme saying, okay, what if you had a hundred thousand pins, full matrix uh contactor, where you had printed carbon fiber, and you combine that with uh MEMS micro actuators that could planarize all of the pins uh in real time?
SPEAKER_03:I would say not to not to uh maybe group of uh mems actuators. Yes. And we do some level of uh you can call it planarization. There's some proprietary thing uh which I can share, I cannot share, but I would say hundreds of thousands of pins with MEMS actuators, probably not, but to the level what is needed from um different dye requirements or even within the dye, uh we we already talk about hybrid probe today, right? Uh so there are different requirements, which is reality, but uh individual actuators, uh that maybe not, right?
SPEAKER_00:Yeah, I was thinking that I don't know if you would need that. And then if you did need it, uh it seems like it would drive up the cost significantly, right? So I mean it would be cool technology, but uh maybe you you don't need that and they solve the planarity issues uh some other way. Yeah.
SPEAKER_03:And like I said, right? Uh uh every design you need a different card now, uh because the design requirements are different. Uh unless you have one constant design which is standard and you use actuators to justify the ROI. I don't see uh physical, practical implementation and whether customers would go for it or not.
SPEAKER_00:Okay, so we'll give GPT a science fiction on that one. Yeah. Okay, the third one is on-card silicon photonics transceivers for co-packaged optics and HPM test. So this is essentially thinking about the probe card itself contains uh the optical transceivers, the gradings, filters, all of that. Yeah, and it's built in.
SPEAKER_03:Sounds like some of that you already do, but that that is more close uh uh to to something that uh you you that is needed on the roadmap, I would say. And there's a lot of attention and uh technology need from the industry too. I would say yes, that is more practical than science fiction.
SPEAKER_00:Oh, I thought that one would be science fiction, but okay.
SPEAKER_03:That one's yeah, but like I said, it implementation is always difficult. Uh the the need makes sense, right? Uh so it's uh yeah, if you put it up in one card, that might be good.
SPEAKER_00:If we can do it cost effectively, I mean it's a long road to get there, I think. But yeah, yeah, it's an interesting idea. Okay, and then the last one was GPT took a term from your marketing at contact intelligence and came up with contact intelligence 2.0. Okay. Uh, which was around self-healing, self-calibrating arrays, basically embedding AI firmware into the probe card that communicates when and what to do uh with with regards to maintenance or serviceability, and maybe even regrowing. I think the term it used is relithiation, where say a pin got damaged or broken, and it would regrow that pin, I guess, in some service uh that's our very futuristic AI thing. But I think it is more this next year.
SPEAKER_03:I I I don't think uh regrowing a pin, then no. I I you know it's it's a great wish list, actually. Yeah. If you think about it, yeah.
SPEAKER_00:You know, like lizard regrows its tail, so you can regrow the pins instead of pulling one out and putting another one in.
SPEAKER_03:I wish probe card was so easy. Uh but but uh you know, some of these AI applications are needed uh from from regrowing a pin. Uh we just talked about the complexity of each of these uh probes that we are talking about. Uh every every technology strength, the probes are getting more and more complex.
SPEAKER_01:Right.
SPEAKER_03:Right. We we have factories and we work on those uh long. You know, the just the processing of these probes also takes uh weeks, right? Regrowing something at a uh at a service center by from a from a wafer somewhere, that that's a far-fetched out. Uh it would be much more easier to to have somebody go and replace it.
SPEAKER_00:Much cheaper, much faster.
SPEAKER_03:Much cheaper, much faster.
SPEAKER_00:Okay. Science fiction on that, GPT. I'm just curious for these most some of the most advanced probe cards, how long does it take to get from the design of a probe card to actually having a probe card where you can use it?
SPEAKER_03:Oh wow, you're gonna put me on spot for that. Uh I think uh it it is uh it varies quite a lot, right? Uh so uh sometimes when you're talking about the new design, um, and it depends whether the customers are gonna do the design, whether we have to do the PCB, MLO design versus the actual car design, right? So time varies on that, but it can range anywhere from eight weeks to twelve weeks. Okay. Some complex design could even take longer. Uh so we talked about high parallelism.
SPEAKER_00:I thought you were gonna say much longer because it's so complicated. Yes.
SPEAKER_03:No, but but high parallelism and everything also takes much longer. Now, what is happening is all the customers they always ask to squeeze everything in as fast as we can. And this is where you can use uh some of these AI applications to help you speed up on uh exactly what I was gonna ask. Yeah. So so there are opportunities where you can speed up uh more onto the design side. And on the factory and operations, uh, we continue to look at that. We continue to uh look at ways to automate it and speed up the process, similar to how the foundry partners are doing. They speed up their process. Uh, we do the same thing on our uh probes uh fabrication process point of view. As a matter of fact, I was gonna segue into the capacity needs, right? Uh so we just acquired uh uh a factory in uh farmer's branch. Uh-huh. Uh we're gonna double down. Uh uh we have about 50,000 square foot of uh clean room space. There's significant need in terms of the overall capacity uh requirement from the customers. So that's one of the reasons we uh we got this factory and we're gonna it's more capacity is needed. Yeah. And and uh that will also help in terms of the overall uh cycle time, lead time that you're talking about.
SPEAKER_00:Yeah, we see that too. You know, we had a little bump in the road earlier this year, but uh things are uh looking pretty good. Yeah, at least uh everything that we're seeing with with customers and what's going on in in the industry. I think it's a it's an interesting market to be in right now. Okay, so that does it for pin count prophecies. Thank thank you for painfully going through that uh with me. No, it was it it was a joy and a pleasure, Ken. I think that was fun. Okay, so what I want to do next, we have the lightning round.
SPEAKER_03:Okay.
SPEAKER_00:I came up with a few questions just to throw at you real quick, and then you can uh whatever comes off the top or comes to the top of your mind, you can talk about that. The first one is the biggest myth about probe cards or the biggest misconception. Go. What what's the biggest myth or misconception about probe?
SPEAKER_03:I'll tell you, it's also something that I had that before. I'm like, yeah, a probe card. You know, you talk about uh micrometers, it should be simple. It's a commodity, voltage and current. It's just like uh pins that touch. But the more you get to know, the more complex it is. Uh so it's not uh as simple commodity as uh many people misinterpret that. And it's a myth that, oh yeah, it's a probe card, backend test, it should be simple, but it's way complex than when people take it. So a lot more thing into you know, cost, commodity. Uh that's how that's what people think about, but it is not. It is way more complex uh technology uh than it appears from outside world.
SPEAKER_00:Yeah, and definitely sounds like it's an enabling technology. You you can't get the products to market without it, so you're a critical path, I would say, but you're juxtaposed against it's a consumable. Yes. Right? So it's consumable, so they don't want to pay for something they're going to end up throwing away, but you absolutely have to have it.
SPEAKER_03:Yeah.
SPEAKER_00:Um, interesting dichotomy that you have there. Um, okay. What the most underrated metric everyone should track, but rarely does. So we we talked about like lifetime or cost. What what do you feel is the most important metric that people don't look at or that that they should look at?
SPEAKER_03:I think uh we we talk a lot about technology, roadmap, and all of that, right? Uh I'm not gonna speak about that, that we collaborate, partner with the customers. I think uh you you're right, in terms of uh quality, uh lifetime repeatability and consistency is uh what is also needed on the probe card because at the end of the day, uh the better quality you have, to me, this is where we can help the customers in terms of MTBF, MTBI, and the cost, right? And getting reliable, consistent uh results with a probe card, I would say that's like most underrated today. Okay. Technology requirements, uh, we can get it covered early enough, but uh people do tend to underrate quality on uh on this aspect.
SPEAKER_00:And could you describe for the audience MTBF and MTBI? What does that mean?
SPEAKER_03:So mean time between failure, mean time between interrupt, what happens is when you're testing uh the wafer and the devices and your card is there. If if you you talked about a pin failure, for example, if a pin fails, uh then you cannot test the wafer. So that means you have wafer sitting on the floor without getting tested. To me, that is the time. And the time costs customers money because you cannot get those dyes out and you cannot sell those dyes to the end consumers. So that that's why, you know, what we talk about, I give reference of front-end process. When a tool is down, you cannot process the wafer. Same thing happens on the back end side. If you cannot test the wafer, the wafer is just sitting there. That's to me, that's quite uh quite uh cost impact to the customer. So having better quality, uh, longitivity, and a support model that we were talking about, that you can respond to the customers faster or have solutions that the wafers are not going to be sitting there. Uh, that's uh something that uh we put focus on, we put emphasis on, and we ensure that we have a policy called first time right, actually. Uh we don't talk about dead and arrival, we talk about first time right, and we put a lot of emphasis on that. Um and it is becoming more key. Otherwise, what happens is if you don't have good quality products and you have to throw people to fix issues in the field. So it's uh better to focus on it up front, make sure that you have good quality products with better mean time between interrupt or failures that saves people money.
SPEAKER_00:I'm sure your customers have heard about it. Yeah. Uh, but that makes a lot of sense. Yeah. Not dead on arrival, but let's make sure everything's first time right. Yes. Okay. Then the last one, I mean, both of us have been in the semiconductor industry for the better part of three decades. What career advice would you give your younger self after traversed not only now the colorful front end and now you're on the more dramatic uh back end? What what sort of advice would you give your younger self?
SPEAKER_03:I would say uh I would split it up into two parts, right? One is getting the breadth of the technology. Um what happens is when you're young, you're so focused on uh on on proving not just to your management, but also to yourself, you can grow. Um and you have the you have the blinders on or blinker uh blinders on and you're just focused on that. I think getting the breadth of technology, uh, and and you always hear this term uh be curious, right? Uh be hungry, be foolish in terms of understanding the I would I would have loved if I had that level of understanding of the entire semiconductor ecosystem back then. Uh so getting more onto the the breadth of it would be one area. The second thing is uh, you know, I'll tell you personally, uh I've gone from uh very hardcore RD where I know what I have to do sitting in the cube to sales side, where I talked to a lot of people. Uh I think uh more onto team collaboration, speaking to people, speaking to people in the industry. That would be the other area that I would advise myself if I was back in 25, but also to the young college kids who are there today, right?
SPEAKER_00:Yeah. You actually triggered another thing. The complexity of the semiconductor industry is enormous. I think everyone would benefit if they had a much broader understanding. Yeah. Like I I have bits and pieces of the front end, but not a really deep understanding of it at all. But now with AI, yeah, you have experts in every topic, every domain. So I'm a bit envious of the new graduates coming out of college because they can actually achieve that because they have these experts so much knowledge sitting right there that know the last 50, 60 years that we would never even if we would have tried to do this, we would never have been able to achieve it because who how would you acquire that knowledge?
SPEAKER_03:Actually, that is true. If he had AI, I I didn't think about it. If he if he had AI back when we were 25, I don't know what advice I would have given to myself. But yes, the knowledge is there. Yeah. Right? Uh it's um it's where you spend your time and uh, you know, which are the directions that you want to grasp. The the the pool of uh resources that are out there today, uh, just enormous.
SPEAKER_00:Is there anything else that you want to cover? No, I think we're good. All right. So that wraps up another episode of Advanced Test Talk Simi. A huge thank you to Ashatosh David for taking us from the early micro spring days through HBM, AI accelerators, and even cryo probe test. So your inside look at how Form Factor Engineers first contact for tomorrow's chips was Equal Parts masterclass and inspiration. So, listeners, if you'd like to dive deeper, replay AstroTosh Teams technical session from Southwest Test 2025, you can catch both Form Factor and Advanced at Semicon West 2025 in Phoenix October 7th through the 9th. You can, of course, see the links to the podcast and the websites and below in the channel. And if today's conversation sparked an idea, share it. You want to comment, do so on the Advanced Test Talk Semi episode with a colleague. Leave us a rating, and of course, be sure to subscribe and never miss a bite of semiconductor insight. So I'm Keith Schubb signing out. Thanks for joining us on Advan Test Talk Simi. Until next time, keep pushing the limits of test. Thank you, Asatosh.
SPEAKER_03:Thank you, Keith.
